Clamping circuit for the VPOP voltage used to program antifuses

ABSTRACT

A booting circuit, used during antifuse programming, that has a clamping circuit designed to prevent a programming voltage from being unnecessarily limited by other components in an integrated circuit. The booting circuit is connected between an external interface, such as a bond pad, and an internal line, and is activated when the programming voltage is being applied directly to the internal line (i.e., not through the external interface). When activated, the clamping circuit allows a suitable and sufficiently high voltage to be applied to the internal line to properly program the antifuses while also clamping the amount of voltage seen at the external interface.

FIELD OF THE INVENTION

[0001] The present invention relates to a clamping circuit for the Vpopvoltage used to program antifuses in an electronic circuit.

BACKGROUND OF THE INVENTION

[0002] There are many electronic circuits or integrated circuits (ICs)that utilize antifuses to set or program a piece of logic to a specificvalue. Antifuses are capacitive-type structures which, in their unblownstate, form open circuits. Antifuses are programmed/blown by applying ahigh voltage across the antifuse. The high voltage causes thecapacitive-type structure to break down, forming a conductive paththrough the antifuse. Therefore, programmed/blown antifuses conductwhile unprogrammed/unblown antifuses do not. One circuit, for example,that uses antifuses is a memory circuit.

[0003] Typical memory circuits include arrays of memory cells arrangedin rows and columns. These memory circuits will also include severalredundant rows and columns that are used as substitutes for defectivelocations in the memory array. When a defective memory array location isidentified, rather than treating the entire array as defective, aredundant row or column is substituted for the defective row or column.This substitution is performed by assigning the address of the defectiverow or column to the redundant row or column such that, when an addresssignal corresponding to the defective row or column is received, theredundant row or column is addressed instead.

[0004] To make the substitution of the redundant row or columnsubstantially transparent to a system including the memory circuit, thememory circuit utilizes an address detection circuit. The addressdetection circuit monitors row and column addresses and enablesredundant rows or columns if the address of a defective row or column isdetected. FIG. 1 illustrates the typical memory circuit 10 including anaddress detection circuit 20, control and address circuitry 12, an arrayof memory cells 14 and row and columns of redundant memory cells 16.

[0005] One type of address detection circuit 20 is a fuse-bank addressdetection circuit. A fuse-bank address detection circuit utilizesseveral fuse-bank circuits to control the redundant rows and columns.Each fuse-bank circuit corresponds to one of the redundant rows orcolumns. If there are eight redundant rows and eight redundant columns,for example, then the address detection circuit 20 will include sixteenfuse-bank circuits. Each fuse-bank circuit includes a bank of senselines, each sense line connected to a respective fuse. Each sense linecorresponds to one bit of a memory address since each fuse-bank will beprogrammed with an address of a defective memory array location. If anaddress comprises eight bits, then each fuse-bank circuit includes eightsense lines, each with corresponding fuses.

[0006] The sense lines are “programmed” by blowing fuses in a patterncorresponding to the address word of the defective row or column(hereinafter referred to as the programmed addresses). The programmedaddresses are then detected by initially applying a test voltage acrossthe bank of sense lines. Then, bits of an external address are appliedto the sense lines. If the pattern of blown fuses corresponds exactly tothe pattern of external bits, a redundant match will be detected and theoutput signal will switch to a high state. Otherwise, if at least oneexternal address bit does not correspond to its respective blown fuse, anon-match will be detected and the output signal will be in a low state.Therefore, a high voltage indicates that the programmed address matchesthe external address while a low voltage does not. A matched addressindicates that the redundant row or column should be used.

[0007] To save the costs and labor required to blow the conventionalfuse, antifuses have replaced fuses in the address detection circuit 20.FIG. 2 illustrates an antifuse circuit 30 used in an antifuse-bankcircuit. The circuit 30 corresponds to one bit of a programmed address.As previously stated, if an address consisted of eight bits, then eachantifuse-bank circuit would include eight antifuse circuits 30. Anantifuse 32, illustrated in its unprogrammed (i.e., unblown) state, isconnected to a switchable signal line often referred to as a commonground line (hereinafter “CGND line) and a latch circuit 34. Duringnormal operation, the CGND line is held at a ground potential to providea reference for the antifuse 32. To program the antifuse 32, the CGNDline is supplied with a high voltage sufficient enough to cause thecapacitive-type structure of the antifuse 32 to break down. Generally,the high voltage used to program the antifuse is referred to as aprogramming voltage (Vpop).

[0008] Once programmed, the antifuse 32 has a known impedance, plus orminus a predetermined margin, which is detected by the latch circuit 34.When strobed by logic in the address detection circuit 20 (FIG. 1), thelatch circuit 34 detects the impedance of the antifuse 32 and outputs anoutput signal that is either a logical “1” if the antifuse is programmedor a logical “0” if the antifuse is not programmed. This output signalwhen combined with the output signals of the remaining antifuse circuits30 of the antifuse-bank circuit forms an address of a defective memorylocation (i.e., a programmed address). The operation of antifuses in anaddress detection circuit 20 is described, for example, in U.S. Pat.Nos. 5,734,617 (Zheng), 5,742,555(Marr et al.), and 5,706,238 (Cutter etal.), all assigned to Micron Technology Inc. and incorporated byreference herein.

[0009] In some ICs, the CGND line is directly accessible before thedevice is packaged (e.g., still in wafer form). During initial testingand repair, the CGND line is connected to directly using a probe card.This is referred to herein as “direct-connect” programming or a firstprogramming mode of operation. In direct-connect programming, the probecard provides the programming voltage Vpop to the CGND line, which isused to program the appropriate antifuse. After the device is packaged,however, the direct connection to the CGND line cannot be made. Becauseit is desirable to make repairs to the packaged product, manufacturerswill include a backdoor mechanism for applying the programming voltageVpop to the internal CGND line from an external device. This is referredto herein as “external” programming or a second programming mode and isprovided via a pin on the external package.

[0010] The backdoor mechanism typically includes a booting circuitconnected between the external connection (i.e., pin/pad) and the CGNDline. During normal operation of the packaged IC, the booting circuitisolates the external pin/pad from the internal CGND line. During a testmode of the packaged part, when it is desirable to program antifuses(i.e., during the second programming mode), the booting circuit receivesthe programming voltage Vpop from the external pin/pad and passes thevoltage Vpop to the CGND line. Typically, the booting circuit uses apass gate transistor to connect the external pad to the CGND line. Thepass gate transistor is “booted” (i.e., has its gate voltagecapacitively driven to an elevated level to turn it on to a preferredstrength (a certain voltage from its gate to its source) and avoid anythreshold voltage loss across the device) by a booting capacitorcircuit.

[0011] Unfortunately, due to the self-booting nature of portions of thebooting circuit, when the unpackaged memory device is being programmedby the directly connected probe (e.g., during direct-connect programmingor first programming mode), the voltage on the CGND line is passed ontothe external pad. This very high voltage is seen across theelectrostatic discharge (ESD) device of the pad, which can breakdown andlimit the programming voltage Vpop. Limiting the programming voltageVpop increases the time required to program the antifuses and decreasesthe resistance distribution in blown antifuses. Both of these sideeffects are undesirable.

[0012] Accordingly, there is a desire and need for a booting circuitthat substantially ensures that the proper voltage is applied to theantifuses during antifuse programming and in particular, duringdirect-connect antifuse programming.

SUMMARY OF THE INVENTION

[0013] The present invention provides a booting circuit, used duringantifuse programming, which substantially ensures that the properprogramming voltage is applied to the antifuses during antifuseprogramming.

[0014] The present invention provides a booting circuit, used duringantifuse programming, which substantially ensures that the properprogramming voltage is applied to the antifuses during direct-connectantifuse programming.

[0015] The above and other features and advantages are achieved by abooting circuit, used during antifuse programming, that has a clampingcircuit designed to prevent a programming voltage from beingunnecessarily limited by other components in a integrated circuit. Thebooting circuit is connected between an external interface, such as abond pad, and an internal line, and is activated when the programmingvoltage is being applied directly to the internal line (i.e., notthrough the external interface). When activated, the clamping circuitallows a suitable and sufficiently high voltage to be applied to theinternal line to properly program the antifuses, yet clamps the amountof voltage seen at the external interface. The clamping prevents ESDbreakdown by the external interface from unnecessarily limiting theprogramming voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The foregoing and other advantages and features of the inventionwill become more apparent from the detailed description of exemplaryembodiments provided below with reference to the accompanying drawingsin which:

[0017]FIG. 1 is a block diagram illustrating a typical redundant memorycircuit;

[0018]FIG. 2 illustrates an antifuse circuit used in the memory circuitillustrated in FIG. 1.

[0019]FIG. 3 illustrates a booting circuit constructed in accordancewith an exemplary embodiment of the invention; and

[0020]FIG. 4 illustrates a processor system incorporating a memorycircuit constructed in accordance with an embodiment of the invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0021] In the following detailed description, reference is made tovarious specific embodiments in which the invention may be practiced.These embodiments are described with sufficient detail to enable thoseskilled in the art to practice the invention, and it is to be understoodthat other embodiments may be employed, and that structural andelectrical changes may be made without departing from the spirit orscope of the present invention.

[0022] In addition, the embodiments of the invention are described asapplied to an SDRAM (synchronous dynamic random access memory). However,the invention is not limited to SDRAMs, and it should be appreciatedthat the invention is equally applied to other memory devices such as,for example, static RAMs (SRAMs), dynamic RAMs (DRAMs), video RAMs(VRAMs), and erasable programmable read only memories (EPROMs). Itshould also be appreciated that the invention is equally applied toother devices or integrated circuits that use and program antifuses suchas processors and controllers.

[0023]FIG. 3 illustrates a booting circuit 100 constructed in accordancewith an exemplary embodiment of the invention. The circuit 100 is usedin an integrated circuit such as a memory device (e.g., SDRAM) andincludes a pass gate transistor 102, a precharge circuit 110, a bootingcapacitor circuit 140 and a clamping circuit 150. The booting circuit100 is connected between a bond pad 104 (via line portion CgndPad) andthe CGND line by the pass gate transistor 102. The bond pad 104 may beany pad suitable for receiving the programming voltage Vpop. Thus, thepad 104 serves as an interface for applying the programming voltage Vpopto the booting circuit 100 from an external source and may be referredto herein as an external interface.

[0024] The precharge circuit 110 includes three inverters 112, 116, 122,a NAND gate 114, five n-channel MOSFET (metal oxide semiconductor fieldeffect transistor) transistors 120, 126, 128, 130, 132 and two p-channelMOSFET transistors 118, 124. The first inverter 112 has its inputconnected to receive a probe signal PROBEttl. The output of the firstinverter 112 is connected to a first input of the NAND gate 114. Thesecond input of the NAND gate 114 is connected to receive an enableprogramming signal ENPROG. The probe signal PROBEttl and the enableprogramming signal ENPROG are used to control the operation of theprecharge circuit 110 (and the clamping circuit 150) as discussed belowin more detail.

[0025] The output of the NAND gate 114 is input by the second inverter116. The output of the second inverter 116 is input by the thirdinverter 122 and is also connected to the gate of the first n-channel120. The first n-channel transistor 120 is connected between a groundpotential and the first p-channel 118. The output of the third inverter122 is connected to the gates of the second and fourth n-channeltransistors 126, 130. The second n-channel transistor 126 is connectedbetween a ground potential and the second p-channel transistor 124. Thefourth n-channel transistor 130 is connected between a ground potentialand the third n-channel transistor 128.

[0026] The first p-channel transistor 118 has its gate connected to theconnection between the second n-channel transistor 126 and the secondp-channel transistor 124. The second p-channel 124 has its gateconnected to the connection between the first n-channel transistor 120and the first p-channel transistor 118. Both of the p-channeltransistors 118, 124 have their source terminals connected to a pumpedvoltage VCCP!. The pumped voltage VCCP! is also applied to the gate ofthe third n-channel transistor 128. The third n-channel transistor 128has its source fed back to its drain and is also connected to the sourceof the fourth n-channel transistor 130. The fifth n-channel transistor132 has its gate connected to the pumped voltage VCCP! and its drainconnected to the connection between the third and fourth n-channeltransistors 128, 130.

[0027] The fifth n-channel transistor 132 is also connected to thebooting capacitor circuit 140 and a node B. As will be discussed belowin more detail, the function of the precharge circuit 110 is prechargethe pass gate transistor 102 to the pumped voltage VCCP!.

[0028] The booting capacitor circuit 140 is connected between the node B(NET160) and the precharge circuit 110 and is also connected to the CGNDline and the clamping circuit 150. In operation, if the clamping circuitwere not present, the booting capacitor circuit 140 would input theprogramming voltage from the CGND line, which then boots the pass gatetransistor 102 (via node B). Booting the pass gate transistor 102 is notdesirable, however, when direct-connect programming is being performedbecause the programming voltage can be passed to the pad 104. As notedabove, ESD devices (or other forms of junction breakdown devices) of thepad 104 can in turn limit the programming voltage, which impacts theantifuse programming operation. Thus, the booting capacitor circuit 140inputs the clamped programming voltage from the clamping circuit 150. Asexplained below, the clamped voltage does not boot the pass gatetransistor 102, which prevents the aforementioned problems.

[0029] The exemplary clamping circuit 150 includes an inverter 152, aNAND gate 154, a series of six diode-connected transistors 156, 158,160, 162, 164, 166, and two n-channel MOSFET transistors 168, 170. Theinput of the inverter 152 is connected to the probe signal PROBEttl. Theoutput of the inverter 152 is connected to a first input of the NANDgate 154. The second input of the NAND gate 154 is connected to theenable programming signal ENPROG. The output of the NAND gate 154 isconnected to the gate terminal of the second n-channel transistor 170.The second n-channel transistor 170 is connected between a groundpotential and the first n-channel transistor 168. The first n-channeltransistor is connected to the series connection of the diode-connectedtransistors 156, 158, 160, 162, 164, 166 and has its gate terminalconnected to the pumped voltage VCCP!.

[0030] The diode-connected transistors 156, 158, 160, 162, 164, 166 areconnected between the CGND line and the first n-channel transistor 168and essentially form a voltage divider circuit for any voltage receivedfrom the CGND line. The diode-connected transistors 156, 158, 160, 162,164, 166 are also connected to node B. The voltage division performed bythe diode-connected transistors 156, 158, 160, 162, 164, 166 reduces thevoltage seen at the booting capacitor circuit 140. In operation, theclamping-circuit 150 is only activated when the enable programmingsignal ENPROG indicates that antifuse programming has been enabled andthe probe signal PROBEttl indicates that programming is being performedby a directly-connected probe card. Otherwise, the clamping circuit 150is disabled.

[0031] The booting circuit 100 operates as follows. When the enableprogramming signal ENPROG indicates that antifuse programming is notenabled, the precharging function of the precharge circuit 110 isdisabled. Because the precharge circuit 110 is disabled, the node B istied to a ground potential. With the node B tied to the groundpotential, the pass gate transistor 102 remains off, which isolates thepad 104 from the CGND line. This situation arises when the packagedSDRAM is in normal operational mode or when testing of the unpackagedSDRAM has been completed. It should be noted that the clamping circuit150 is also disabled at this point.

[0032] When the enable programming signal ENPROG indicates that antifuseprogramming is enabled, the precharging function of the prechargecircuit 110 is activated, but depending upon the state of the probesignal PROBEttl, the clamping circuit 150 may or may not be activated.If the probe signal PROBEttl indicates that a directly-connected probeis not being used to supply the programming voltage, then the clampingcircuit 150 is disabled. The precharge circuit 110, however, prechargesthe node B to the pumped voltage VCCP! and when the pad 104 is broughtup to the programming voltage Vpop, the voltage at the node B and passgate transistor 102 are self-booted (via the booting capacitor circuit140). Once booted, the pass gate transistor 102 allows the programmingvoltage Vpop to pass from the pad 104 to the CGND line. It should benoted that this scenario only arises when the internal CGND line cannotbe directly-connected to a probe, such as when the SDRAM has beenpackaged and the device is in the second programming mode.

[0033] When the enable programming signal ENPROG indicates that antifuseprogramming is enabled and the probe signal PROBEttl indicates that adirectly-connected probe is being used to supply the programmingvoltage, then both the precharge circuit 110 and the clamping circuit150 are activated. This is the first programming mode described above.Under these circumstances, the node B is precharged to the pumpedvoltage VCCP! by the precharge circuit 110, but when the CGND line isbrought up to the programming voltage Vpop, the voltage seen at the nodeB is clamped by the clamping circuit 150. Because the voltage seen atthe node B is clamped, the pass gate transistor 102 does not get bootedand thus, does not pass the full programming voltage Vpop to the pad104. Thus, the pad 104 does not receive the full level of theprogramming voltage Vpop, but the CGND line does. Because the pad 104does not receive the full programming voltage Vpop, its ESD devices donot unnecessarily limit the voltage. As such, the full programmingvoltage Vpop can be applied to the antifuses (via the CGND line), whichdecreases the time required to program the antifuses and increases theresistance distribution in the programmed/blown antifuses—both of whichare desirable and unachievable in prior art devices.

[0034] It should be noted that the clamping circuit 150 illustrated inFIG. 3 is one example of how to implement clamping in the bootingcircuit 100. Those skilled in the art will appreciate that the precisecircuitry used in the clamping circuit 150 is not important as long asthe circuitry used can clamp the programming voltage when required. Itshould also be appreciated that the illustrated circuitry for theprecharge circuit 110 is merely one example of how to precharge the nodeB and that the invention is not to be limited to a particularconfiguration of the precharge circuit 110.

[0035]FIG. 4 illustrates a processor system 500 incorporating a memorycircuit 512 constructed in accordance with an embodiment of theinvention. That is, the memory circuit 512 comprises a booting circuit100 designed to substantially ensure that the programming voltage Vpopis not unnecessarily limited during the direct-connect programmingoperation as explained above with respect to FIG. 3. The system 500 maybe a computer system, a process control system or any other systememploying a processor and associated memory.

[0036] The system 500 includes a central processing unit (CPU) 502,e.g., a microprocessor, that communicates with the DRAM memory circuit512 and an I/O device 508 over a bus 520. It must be noted that the bus520 may be a series of buses and bridges commonly used in a processorsystem, but for convenience purposes only, the bus 520 has beenillustrated as a single bus. A second I/O device 510 is illustrated, butis not necessary to practice the invention. The system 500 may alsoinclude additional memory devices such as a read-only memory (ROM)device 514, and peripheral devices such as a floppy disk drive 504 and acompact disk (CD) ROM drive 506 that also communicates with the CPU 502over the bus 520 as is well known in the art. It should be noted thatthe memory 512 may be embedded on the same chip as the CPU 502 if sodesired.

[0037] While the invention has been described and illustrated withreference to exemplary embodiments, many variations can be made andequivalents substituted without departing from the spirit or scope ofthe invention. Accordingly, the invention is not to be understood asbeing limited by the foregoing description, but is only limited by thescope of the appended claims.

What is claimed as new and desired to be protected by Letters Patent ofthe United States is:
 1. A booting circuit connecting an externalinterface to an internal line of a device, the line being adapted tosupply a programming voltage to a programmable element in the deviceduring a programming operation, said booting circuit comprising: aprecharge circuit having a precharge output responsive to a plurality ofcontrol signals; a clamping circuit responsive to said control signalsand being adapted to receive the programming voltage from the line, saidclamping circuit outputting a clamped programming voltage when activatedby said control signals; a first circuit connected to the line and saidclamping circuit, said first circuit having a first output having afirst voltage level based on the programming voltage or a second voltagelevel based on the clamped programming voltage; and a bootable elementconnected between the external interface and the internal line, saidbootable element being controlled by said precharge output and the firstoutput to allow the programming voltage to be directly applied to theline while preventing a full level of the programming voltage from beingsent to the external interface during a first programming mode.
 2. Thebooting circuit of claim 1, wherein said clamping circuit comprises avoltage divider circuit that is activated when said control signals areindicative of the first programming mode.
 3. The booting circuit ofclaim 1, wherein clamping circuit comprises: an inverter adapted toreceive a first control signal, said inverter having a second output; aNAND gate adapted to receive a second control signal and said secondoutput, said NAND gate having a third output; a first switchable elementconnected to said third output; and a plurality of resistive elementsconnected between said third output and said line, wherein saidresistive elements are switched into said clamping circuit when saidcontrol signals are indicative of the first programming mode.
 4. Thebooting circuit of claim 3, wherein said resistive elements comprisesdiode-connected transistors.
 5. The booting circuit of claim 1, whereinsaid bootable element is controlled by said precharge output and thefirst output to isolate the external interface from the line duringnormal operation of the device.
 6. The booting circuit of claim 5,wherein said precharge output is a ground potential when said controlsignals are indicative of a normal operating mode of the device.
 7. Thebooting circuit of claim 1, wherein said bootable element is controlledby said precharge output and the first output to pass an externallysupplied program voltage from the external interface to the line duringa second programming mode of the device.
 8. The booting circuit of claim7, wherein said precharge output is a pumped potential when said controlsignals are indicative of the second programming mode.
 9. The bootingcircuit of claim 7, wherein said first output is said first level whensaid control signals are indicative of the second programming mode. 10.The booting circuit of claim 1, wherein said precharge output is apumped potential when said control signals are indicative of aprogramming mode of the device.
 11. The booting circuit of claim 1,wherein said first output is said second level when said control signalsare indicative of the first programming mode.
 12. The booting circuit ofclaim 1, wherein said bootable element is a transistor.
 13. The bootingcircuit of claim 1, wherein said first circuit comprises a bootingcapacitor circuit.
 14. A memory device comprising: an externalinterface; a signal line adapted to supply a programming voltage to aprogrammable element in said device; a booting circuit connected betweensaid external interface and said signal line, said booting circuitcomprising: a precharge circuit having a precharge output responsive tofirst and second control signals; a clamping circuit responsive to saidcontrol signals and being adapted to receive the programming voltagefrom said signal line, said clamping circuit outputting a clampedprogramming voltage when activated by said control signals; a firstcircuit connected to said signal line and said clamping circuit, saidfirst circuit having a first output based on the programming voltage orthe clamped programming voltage; and a bootable element connectedbetween said external interface and said signal line, said bootableelement being controlled by said precharge output and said first outputto allow the programming voltage to be directly applied to said signalline while preventing a full level of the programming voltage from beingpassed to said external interface during a first programming mode. 15.The memory device of claim 14, wherein said clamping circuit comprises avoltage divider circuit that is activated when said control signals areindicative of the first programming mode.
 16. The memory device of claim14, wherein clamping circuit comprises: an inverter adapted to receive afirst control signal, said inverter having a second output; a NAND gateadapted to receive a second control signal and said second output, saidNAND gate having a third output; a first switchable element connected tosaid third output; and a plurality of resistive elements connectedbetween said third output and said signal line, wherein said resistiveelements are switched into said clamping circuit when said controlsignals are indicative of the first programming mode.
 17. The memorydevice of claim 16, wherein said resistive elements comprisesdiode-connected transistors.
 18. The memory device of claim 14, whereinsaid bootable element is controlled by said precharge output and thefirst output to isolate said external interface from said signal lineduring normal operation of said memory device.
 19. The memory device ofclaim 18, wherein said precharge output is a ground potential when saidcontrol signals are indicative of a normal operating mode of said memorydevice.
 20. The memory device of claim 14, wherein said bootable elementis controlled by said precharge output and the first output to pass anexternally supplied program voltage from said external interface to saidsignal line during a second programming mode of said memory device. 21.The memory device of claim 20, wherein said precharge output is a pumpedpotential when said control signals are indicative of the secondprogramming mode.
 22. The memory device of claim 14, wherein saidprecharge output is a pumped potential when said control signals areindicative of a programming mode of said memory device.
 23. The memorydevice of claim 14, wherein said bootable element is a transistor. 24.The memory device of claim 14, wherein said first circuit comprises abooting capacitor circuit.
 25. The memory device of claim 14, whereinsaid external interface is a bond pad.
 26. A memory device comprising:an external programming pin; an internal line that is programmable by avoltage received from said external programming pin and by a voltagereceived from another source; and a booting circuit for selectivelycoupling said external programming pin with said internal line to allowsaid internal line to be programmed by a first voltage received by saidexternal programming pin and for uncoupling said external programmingpin from said internal line to allow said internal line to be programmedwith a second voltage from said another source, said booting circuitensuring that said internal line is programmed with a full voltage levelof said first and second voltages.
 27. The memory device of claim 26,wherein said booting circuit comprises a clamping circuit for limiting alevel of said second voltage as applied to said external programmingpin.
 28. The memory device of claim 27, wherein said clamping circuit isactivated during a first programming mode of said memory device.
 29. Thememory device of claim 28, wherein said booting circuit allows saidinternal line to be programmed by said first voltage during a secondprogramming mode of said memory device.
 30. The memory device of claim27, wherein said clamping circuit comprises a voltage divider circuit.31. A processor system comprising: a processor; and a memory devicecoupled to said processor, said memory device comprising an externalinterface, a signal line adapted to supply a programming voltage to aprogrammable element in said device, and a booting circuit connectedbetween said external interface and said signal line, said bootingcircuit comprising: a precharge circuit having a precharge outputresponsive to first and second control signals; a clamping circuitresponsive to said control signals and being adapted to receive theprogramming voltage from said signal line, said clamping circuitoutputting a clamped programming voltage when activated by said controlsignals; a first circuit connected to said signal line and said clampingcircuit, said first circuit having a first output based on theprogramming voltage or the clamped programming voltage; and a bootableelement connected between said external interface and said signal line,said bootable element being controlled by said precharge output and saidfirst output to allow the programming voltage to be directly applied tosaid signal line while preventing a full level of the programmingvoltage from reaching said external interface during a first programmingmode.
 32. The system of claim 31, wherein said clamping circuitcomprises a voltage divider circuit that is activated when said controlsignals are indicative of the first programming mode.
 33. The system ofclaim 31, wherein clamping circuit comprises: an inverter adapted toreceive a first control signal, said inverter having a second output; aNAND gate adapted to receive a second control signal and said secondoutput, said NAND gate having a third output; a first switchable elementconnected to said third output; and a plurality of resistive elementsconnected between said third output and said signal line, wherein saidresistive elements are switched into said clamping circuit when saidcontrol signals are indicative of the first programming mode.
 34. Thesystem of claim 33, wherein said resistive elements comprisesdiode-connected transistors.
 35. The system of claim 31, wherein saidbootable element is controlled by said precharge output and the firstoutput to isolate said external interface from said signal line duringnormal operation of said memory device.
 36. The system of claim 35,wherein said precharge output is a ground to potential when said controlsignals are indicative of a normal operating mode of said memory device.37. The system of claim 31, wherein said bootable element is controlledby said precharge output and the first output to pass an externallysupplied program voltage from said external interface to said signalline during a second programming mode of said memory device.
 38. Thesystem of claim 37, wherein said precharge output is a pumped potentialwhen said control signals are indicative of the second programming mode.39. The system of claim 31, wherein said precharge output is a pumpedpotential when said control signals are indicative of a programming modeof said memory device.
 40. The system of claim 31, wherein said bootableelement is a transistor.
 41. The system of claim 31, wherein said firstcircuit comprises a booting capacitor circuit.
 42. The system of claim31, wherein said external interface is a bond pad.
 43. A processorsystem comprising: a processor; and a memory device coupled to saidprocessor, said memory device comprising: an external programming pin,an internal line that is programmable by a voltage received from saidexternal programming pin and by a voltage received from another source,and a booting circuit for selectively coupling said external programmingpin with said internal line to allow said internal line to be programmedby a first voltage received by said external programming pin and foruncoupling said external programming pin from said internal line toallow said internal line to be programmed with a second voltage fromsaid another source, said booting circuit ensuring that said internalline is programmed with a full voltage level of said first and secondvoltages.
 44. The system of claim 43, wherein said booting circuitcomprises a clamping circuit for limiting a level of said second voltageas applied to said external programming pin.
 45. The system of claim 44,wherein said clamping circuit is activated during a first programmingmode of said memory device.
 46. The system of claim 45, wherein saidbooting circuit allows said internal line to be programmed by said firstvoltage during a second programming mode of said memory device.
 47. Thesystem of claim 44, wherein said clamping circuit comprises a voltagedivider circuit.
 48. A method of programming a programmable element in amemory device, said method comprising the steps of: inputting theprogramming voltage; inputting control signals indicative of anoperational mode of the memory device; determining from said controlsignals whether the program voltage is being input from an externalinterface or from an internal signal line in the memory device; and ifit is determined that the program voltage is being input from theinternal signal line, preventing the program voltage from being sent tothe external interface while allowing the program voltage to reach theprogrammable element.
 49. The method of claim 48, further comprising thestep of passing the programming voltage to the signal line if it isdetermined that the program voltage is being input from the externalinterface.
 50. The method of claim 49, wherein said step of inputtingthe programming voltage comprises inputting the programming voltage froma bond pad of the memory device.
 51. The method of claim 48, whereinsaid step of inputting the programming voltage comprises inputting theprogramming voltage from a probe being applied directly to the signalline.